System Verilog

1. Universal Verification Methodology (UVM) – Level 1
2. Class Details
3. Trainers Profiles (Srinivasan Venkataramanan, CTO & Ajeetha Kumari, CEO and MD)
4. Why CVC?
5. Our Global Footprint
6. Other Relevant Courses
7. Customer Set (Sub-Set)
8. Course Content

AGENDA – DAY 1

Session 1 : SV Basics
Session 2 : Interface
Session 3 : Class & BFM

DAY2

Session 4 : OOP Concepts
Session 5 : Concurrency modeling
Session 6 : Constraint random verification

DAY3

Session 7 : Assertion based verification
Session 8 : Coverage driven verification
Session 9 Direct programming interface

9. Registration

CVC’s Verification Using SystemVerilog course gives you an in-depth introduction to the main enhancements that SystemVerilog offers for test bench development, discussing the benefits and issues with the new features.

It also demonstrates how verification is more efficiently and effectively done using SystemVerilog constructs. The course explores in depth verification enhancements such as object-oriented design, constraint random generation, and functional coverage.

Duration: 3-days full time (Can be extended up-to 5 days on need basis)
Prerequisites: Design, Simulation, Synthesis and Verilog
Enrolling for a class: Please refer to Registration section

Srinivasan Venkataramanan, CTO
View On LinkedIn

– Over 20+ years of experience in VLSI Design & Verification

– Designed, verified and lead several multi-million ASICs in image processing, networking and communication domain

– Worked at Philips, Intel, and Synopsysin various capacities. Co-authored leading books in the Verification domain

– Presented papers, tutorials in various conferences, publications and avenues

– Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDV and OOP for Verification

– Holds M.Tech in VLSI Design from prestigious IIT, Delhi

Ajeetha Kumari, CEO AND MD
View On LinkedIn

– Has 18+ years of experience in Verification

– Implemented, architected several verification environments for block & subsystems

– Co-authored leading books in the Verification domain

– Presented papers, tutorials in various conferences, publications and avenues

– Has worked with all leading edge simulators and formal verification (Model Checking) tools

– Conducted workshops and trainings on PSL, SVA, SV, OVM, E, ABV, CDV and OOP for Verification

– Holds M.S.E.E. from prestigious IIT, Madras

– SystemVerilog
– UVM Level 1 (Basic)
– UVM Level 2 (Intermediate)
– UVM Level 3 (Expert)
– UVM RAL
– Art of Debugging with UVM
– ABV-UVM
– Go2UVM
– Graph Based Verification
– Formal Verification

What is SystemVerilog?

SystemVerilog is a major extension to Verilog-2001, adding significant new features to Verilog for verification, design and synthesis.

Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of a complete Object-Oriented Programming feature. There are also considerable improvements in the usability of Verilog for RTL design.

DAY 1

Session 1 : SV BASICS

Introduction to SystemVerilog
– Language evolution
– SV Design
– SV Assertions
– SV Testbench
– DPI and API
Abstract Modeling Constructs
– Data Types
Enums
Structure
– Packages
Arrays
Fixed arrays
Dynamic Arrays
Queues
Associative Arrays
Array methods
Lab 1 – SV Basics

Session 2 : INTERFACE

DUT Description
– Will use a memory controller slave model as DUT
– Uses a proprietary “VLB” (VerifLabs Bus) interface during training
– For AMS – will add few dummy analog/real ports with minimal logic to showcase SV features
Interface
– Grouping signals
– Modport
– Clocking block
LAB 2 – SV Interface
– Manual interface coding
– Automating interface generation

Session 3 : CLASS & BFM

Class
– Introduction to classes
– New – Constructor
– Transaction modelling with class
– Virtual interface
– Building BFM with SystemVerilog class

LAB 3 – Transactions & BFM
– Transaction modeling
– BFM building
– Simple testcase using BFM

Day 2

Session 4 : OOP CONCEPTS

OOP Concepts
– Encapsulation
– Inheritance
– Polymorphism
– Automatic garbage collection
– Task & Function (Automatic & static, void, extern and argument pass by value/reference
Final block
LAB 4 – Classes & OOP
– Inheritance
– Polymorphism

Session 5 : CONCURRENCY MODELING

Enhanced Concurrency Modelling
– Threads variants of fork join
– Disable fork, terminate
Inter process communication
– Mailboxes (Standard API or using it as conduit across classes/components)
Semaphores
– Standard API
– Typical applications
LAB 5 – Threads & Mailbox usage
– Adding mailbox to Driver BFM
– Using Mailbox to drive traffic to DUT
– Adding a monitor component and a new free running thread
– Adding Monitor mailbox

Session 6 : CONSTRAINT RANDOM VERIFICATION

Random vs. Directed testing
Need for Random testing
– Constraints in SVTB
– Class based constraints
– Randomise success / fail
– Inline constraints – randomise with()
– Distribution
– Function calls in constraints
– Array constraints
– Inheritance & layered constraints
Pre / Post randomize
LAB 6 – CRV (Constrained Random Verification)
– Adding constraints to transaction model
– Adding a generator component (another free running thread)
– Connect GEN – to – Driver using Mailbox

Day 3

Session 7 : ASSERTION BASED VERIFICATION

Introduction to Assertions & ABV
Structure of an assertion
Types of assertions
– Immediate
– Concurrent
Verification Directives
– Assert
– Assume
– Cover
– Bind
Boolean layer
– System functions
– Sample value functions
Sequences
– Anatomy
– Delay operators
– Repetition operators
Properties
– Anatomy
– Implication operators
SV scheduling semantics
LAB 7 – ABV (Assertion Based Verification)
– Simple assertions, binding
– Developing checker for given DUT using SVA

Session 8 : COVERAGE DRIVEN VERIFICATION

Functional coverage
– Motivation
– Introduction
– Types of coverage
– Functional coverage process
– Covergroup
– Coverpoint
– Concept of binning
– Cross
– Sampling event

LAB 8 – CDV (Coverage Driven Verification)
– Capturing Functional Coverage Model for the given DUT
– Adding proper sampling
– Run tests, collect coverage, analyze, improve

Session 9 : DIRECT PROGRAMMING INTERFACE

DPI
– Import
– Export
– Context
DPI vs. VPI/PLI
LAB 9 – DPI
– Using simple import & export
– Integrating a C golden Reference Model to a scoreboard via DPI
– Dynamic FCOV query API lab

Send us the following details:

– Name, Email, Contact number of all attendees
– A coordinator name (In case of multiple attendees)
– Training module you are looking for
– On-Site or at CVC premises
– Tentative Schedule – Month & Week (Indicate when your team is available to attend the training)
– You may email the details to training@cvcblr.com or fill in our contact form, or call us on +91-962 020 9223