Art of Debugging with UVM

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       Universal Verification Methodology (UVM) is the industry standard verification methodology for Verification using SystemVerilog (SV). UVM provides means of doing verification in a well-defined and structured way. It is a culmination of well-known ideas, thoughts and best practices. Given the major adoption of UVM across the globe and across the industry, advanced users are looking for tips and tricks to improve their productivity. While UVM does define a structured framework for building complex testbenches, given the strong OOP nature of UVM (and underlying SystemVerilog) and the relatively less familiar audience (as many Design-Verification, DV engineers come from hardware, electronics background and not a heavy Software background), it gets tricky for users to debug UVM based testbenches when things do not work as expected. CVC’s “Art of Debugging with UVM” course gives you hands-on experience with some of the typical UVM debugging scenarios. Split into compile and run-time the course covers the breadth and depth of UVM use cases so that attendees are guaranteed to become more productive with UVM at the end of the course.

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