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SystemVerilog Soft constraints usage in `uvm_do_with macro

Recently we were asked a good & interesting question: How do I use “soft constraint” in the macro `uvm_do_with? What would be the syntax? I say this is a good & interesting

Smart one-liner for bit inversion in SystemVerilog

Recently one of CVC’s successful alumni, Harshal posted a nice challenge for SystemVerilog newcomers. Harshal has gone through our time trusted, long term SystemVerilog course and got placed at Synopsys and his

Test Specification Language – the past, present and the future

At DVCon-14, leading EDA vendor MENT has taken the initiative to propose a Test Specification Standard (see: http://www.goo.gl/BKuNEd ). Given that SV & UVM are well established and deep into their development,

Which SystemVerilog LRM do you refer to?

As we get to the end of an eventful 2013 and look forward to a great 2014, TeamCVC is at Manipal, a beautiful coastal town in the West coast of India. Surrounded

Is your RTL Linter makes you find needle in the haystack? Here is a smarter approach!

  Static design verification through thorough RTL analysis started several years ago, with early stage ones simply being “linters” and the later, advanced ones combining some of formal techniques as well. One

SystemVerilog-VMM to UVM migration – first step

In one of our recently concluded UVM training sessions at CVC a customer asked how easy is it to migrate an existing proven code base running with VMM to UVM. Since this

Invitation to contribute to next generation Verification standard – join the eWG

To all the ASIC Verification enthusiasts interested in pushing the limits beyond existing languages and methodologies, here is your chance to contribute and be part of the change. As many would be

SystemVerilog UVM comparer – hidden gem in show_max

Recently a customer sought a help on how does the UVM’s built-in scoreboard mechanism works, specifically in_order and algorithmic comparators. While he was able to use them well in his design, it

Quick start on ABV for VHDL designers – OVL + VHDL + Modelsim

Recently an ABV early stage user/explorer realized it is little hard to get started with OVL-VHDL-Modelsim combination. It surprised us as  it would many others in the industry, having known how well

Making Verilog simulations a fun and useful game – welcome to EDAPlayground

Victor Lyuboslavsky, Victor EDA, technology partner, guest blogger at CVC Ever wondered if you can run Verilog Sims from a Web Browser? Well, playing with Verilog and OVL has gotten a little